AI-assisted IC design flow skills — specification, RTL, lint/CDC, simulation, synthesis, timing analysis, and signoff
The plugin will be installed here. Keep web if you are unsure.
npx -y @deepseek-ai/dsh plugin --profile web add github:chipweaver/veripower#c8808816711be97337af787db9eb36c7a13f3fde
Compatibility and provenance
Veripower is published as veripower and currently resolves to version 0.2.5. The Hub verifies its manifest and preserves the exact installation source for reproducible installs.
Chip front-end design and verification with coding agents
VeriPower is an open-source plugin for chip front-end design and verification. Working from your specification, a coding agent develops RTL and a UVM testbench, runs EDA tools, and revises the design based on their results. VeriPower manages the work across stages, keeping track of what has passed and what needs to run again.
Each stage has a skill containing instructions and supporting scripts. The agent follows the skill to carry out the work, while a workflow engine records the result and selects what should run next. When a check fails, the agent investigates the cause and the engine schedules the repair.
Each run records the versions of its input and output files. The engine compares these with the current files to determine which results still apply and which checks need to be repeated. An RTL edit requires simulation, lint/CDC, and synthesis to run again, while a testbench edit leaves lint/CDC results intact. The files and execution history are stored on disk, allowing work to resume in a new session.
The verification plan and reference model are based on the specification. Stage scripts verify that every planned test ran and passed, and check coverage, timing, and power against the specified targets. Independent model reviews examine whether the test stimulus and checking logic can detect incorrect behavior. Together, these checks and reviews determine whether a stage passes.
Before the flow completes, the engine checks that all required stages have passed and their results still apply. The generated RTL, testbench, constraints, and reports are available in the project directory.
The flow covers eight stages, from specification to power analysis. Simulation triage is a separate task that investigates simulation failures when the cause is unclear.
The included skills use Synopsys SpyGlass for lint and CDC, Design Compiler for synthesis, PrimeTime for timing and power analysis, and VCS with UVM for simulation.
Results
Three front-end design tasks, bare Claude Code vs. Claude Code + VeriPower. Same LLM, same spec, same EDA tools.
Benchmark
Scale
Baseline
+ VeriPower
gateGPT — fixed-point GPT inference
346K gates
3 of 4 coverage metrics below 90%
pass
FSA — FlashAttention accelerator
32K gates
2 unresolved CDC violations
pass
Coral-NPU — RISC-V ML accelerator
3.4M gates
6/19 tests
19/19
Across these tasks, VeriPower closes verification gaps in coverage, CDC and test execution.
Quickstart
Claude Code
claude plugin marketplace add chipweaver/veripower
claude plugin install veripower@chipweaver
Or point at a working copy: claude --plugin-dir /path/to/veripower.
opencode 1.18.30 has a default 32,000-token completion ceiling. For models that support
longer output, set the second flag to the model's declared output limit; 131072 is
an example.
Launch with codex --enable hooks --enable multi_agent, review the two VeriPower hooks in
/hooks, and start a new session. The plugin uses native subagents and preserves the host's
permission configuration. See Codex setup and runtime behavior.
Ask it to list its skills — the twelve VeriPower ones confirm the install.
Run the brainstorm skill to settle requirements first, then tell the agent:
